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The Design of Low-area 32-bit AES Encryption/Decryption System on FPGA

Posted on:June 20, 2011 at 08:29 PM

The Design of Low-area 32-bit AES Encryption/Decryption System on FPGA

Author: Wattanit Hortrakool, AAI AlHarbiy, Ji Song, Xiao-Yang Ji, Yu-Ou Jiang

Department of Electrical and Electronic Engineering, University of Sheffield

This work is a part of my coursework. It’s unpublished yet and post here under the Creative Commons Attribution-ShareAlike 3.0 Unported License.

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